Serial memory devices typically have a single input pin and a single output pin for providing I/O. Although there are many product specific and proprietary protocols for accessing such devices, many industry standards are known and are in the public domain. For example, I.sup.2 C is a two wire standard, Microwire is a three wire standard, and the serial peripheral interface (SPI) is a four wire standard.
An advantage of using a non-standard protocol is that the memory device and its interface can be custom designed to provide very high speed access. However, the sacrifice is that such devices are typically suited for very specific applications and thus not readily adapted for general use. More importantly, with such devices there is now only a single vendor of the device. On the other hand, a standard interface such as SPI offers the advantages of a universal interface. Such an approach, however, typically results in a device having less than optimal performance characteristics.
In accordance with the specification for reading out memory in SPI compliant devices the address bits of the target memory location are serially shifted in on each rising clock edge, starting with the most significant bit. After clocking in the last address bit the most significant bit of the target byte is latched out on the falling clock edge immediately following the last address bit. Thus, from the time the device receives the last bit of the address, roughly one-half of a clock cycle is available for the following sequence of events to occur: the memory page must be selected; the bits of the selected byte within the page must be sensed; and the most significant bit must be ready to be clocked out.
Each of these events incurs a delay. For example, capacitive loading imposes a delay due to the time needed to charge up the selected word line and the data lines of the selected memory location. Additional time then is needed for the sense amps to detect the state of each of the data lines (i.e. bits) comprising the memory location. This series of events imposes an upper limit on the frequency of operation of the device. The clock frequency cannot exceed the period of time needed to allow for line charging and sense amp operation. Currently, this upper limit is on the order of 2 MHz-5 MHz.
An attempt to increase the read access speed of a serial memory is disclosed in U.S. Pat. No. 5,663,922. The '922 patent discloses a serial memory device wherein the memory array is decomposed into two half-arrays (M1, M2, FIG. 1). Upon receiving all but the last bit of an address, each half-array is accessed to produce a byte therefrom. Each half-array has associated read circuitry (SA1, SA2) for sensing the eight bits comprising a byte, namely a bank of eight sense amps for each half-array. The outputs of the read circuitry feed into a multiplexer (MUX's). The multiplexer controlled to assert the appropriate byte based upon the last address bit received.
A point worth noting in the '922 patent is that additional circuitry is required to support a memory array that is divided into a multiplicity of sub-arrays. This adds to the complexity and the cost of manufacturing such a device. More significantly, a bank of sense amplifiers is needed for each sub-array to sense the accessed byte in that sub-array. Sense amplifiers are notorious for their consumption both of silicon real estate and power. Thus, while the device of the '922 patent offers some reduction in read access time, the size and power burdens of the circuitry which provides such capability outweigh the benefits realized by the circuitry.
What is needed is high speed read access in a serial memory which can be achieved without excessive circuitry. It is a further desire to provide such capability without excessive power requirements.